Modern computer systems require faster, more sophisticated, and larger capacity memory, often provided on daughter cards such as DIMMs (dual-inline memory modules) having a plurality of memory chips per daughter card. As system performance keeps increasing, it is difficult and expensive to connect enough memory parts more or less directly to the processor or its interface ICs. Electrical issues and pin limitations push memory system design in directions that put the memory controller(s) on the memory cards and also push the card interface to have higher data rates per pin in order to reduce the number of pins while keeping the card bandwidth in line with the higher performance needs of the attached processors and of the bandwidth of the memory components on the memory cards. A memory card design that adopts this direction has test issues, in that the memory components (the chips) are not directly accessible for testing as is normal in past industry practice, and the data rates of the high-speed interfaces are too fast for connection to testers that are available in normal production testing. While special purpose test equipment can be built and used, the design of special-purpose memory testers is very expensive and time consuming.
Thus, there is a need for improved testing methods and apparatus for new memory cards and for logic functions in which test access is ‘hidden’ behind high speed interfaces.